Erweiterte HDL-Synthese und Soc-Prototyping: RTL-Design mit Verilog [gebunden]
171,96 €
He completed his M.Tech. He has over 15 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
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