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Logikdesign und Verifizierung mit Systemverilog, Taschenbuch von Thomas, Donal...

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It is directed at: • students currently in an introductory logic design course that also teaches SystemVerilog, • designers who want to update their skills from Verilog or VHDL, and • students in VLSI design and advanced logic design courses that include verification as well as design topics.

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Book Title:

Logic Design and Verification Using Systemverilog
ISBN:

9781523364022

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Standard International Shipping 18,63 EUR - Lieferung zwischen 25. June 2025 und 07. July 2025 (bei heutigem Zahlungseingang)
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