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Low Power Direct Digital Frequency Synthesizer Using FPGA: Design,Simulation,and

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In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The power consumption is 0.396 W at 100MHz clock frequency. The Spurious-Free Dynamic Range (SFDR) is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.

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ISBN-13:

9783639261974
Book Title:

Low Power Direct Digital Frequency Synthesizer Using FPGA
ISBN:

9783639261974

None:

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