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On-Chip Trainings-NPU - Algorithmus, Architektur und SoC-Design von Donghyeon Han

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Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

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EAN:

9783031342363
UPC:

9783031342363
ISBN:

9783031342363
Format:

Hardback, 237 pages, 2023 Edition
Author:

Donghyeon Han
Book Title:

On-Chip Training NPU - Algorithm, Architecture and
Item Height:

1.6 cm
Item Length:

23.4 cm
Item Weight:

0.55 kg
Item Width:

15.6 cm
Language:

Eng
Publisher:

Springer International Publishing AG

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On-Chip Trainings-NPU - Algorithmus, Architektur und SoC-Design von Donghyeon Han

On-Chip Training NPU - Algorithm, Architecture and SoC Design - 9783031342363

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On-chip Training Npu - Algorithm, Architecture and Soc Design, Hardcover by H...

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algorithm design

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On-Chip Trainings-NPU - Algorithmus, Architektur und SoC-Design von Donghyeon Han

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