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On-Chip Training NPU - Algorithm, Architecture and SoC Design by Donghyeon Han H

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By Donghyeon Han, Hoi-Jun Yoo. On-Chip Training NPU - Algorithm, Architecture and SoC Design. Chapter 1 Introduction. - Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching.

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Format:

Hardcover
ISBN-13:

9783031342363
Author:

Donghyeon Han, Hoi-Jun Yoo
Book Title:

On-Chip Training NPU - Algorithm, Architecture and SoC Design
ISBN:

9783031342363

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