Writing Testbenches: Functional Verification of HDL Models by Janick Bergeron (E
123,05 €
Writing Testbenches. What is Verification?. - Verification Tools. - The Verification Plan. - Stimulus and Response. - Architecting Testbenches. "The bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process.".
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